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24-bit, 156 ksps, 112 db - adc with on-chip buffers and serial interface ad7765 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features high performance 24-bit -? adc 115 db dynamic range at 78 khz output data rate 112 db dynamic range at 156 khz output data rate 156 khz maximum fully filtered output word rate pin-selectable oversampling rate (128 and 256) low power mode flexible spi fully differential modulator input on-chip differential amplifier for signal buffering on-chip reference buffer full band low-pass finite impulse response (fir) filter overrange alert pin digital gain correction registers power-down mode synchronization of multiple devices via sync pin daisy chaining applications data acquisition systems vibration analysis instrumentation general description the ad7765 is a high performance, 24-bit - analog-to-digital converter (adc). it combines wide input bandwidth, high speed, and performance of 112 db dynamic range at a 156 khz output data rate. with excellent dc specifications, the converter is ideal for high speed data acquisition of ac signals where dc data is also required. using the ad7765 eases the front-end antialias filtering requirements, simplifying the design process significantly. the ad7765 offers pin-selectable decimation rates of 128 and 256. other features include an integrated buffer to drive the reference as well as a fully differential amplifier to buffer and level shift the input to the modulator. an overrange alert pin indicates when an input signal has exceeded the acceptable range. the addition of internal gain and internal overrange registers make the ad7765 a compact, highly integrated data acquisition device requiring minimal peripheral components. the ad7765 also offers a low power mode, significantly reducing power dissipation without reducing the output data rate or available input bandwidth. functional block diagram refgnd v ref + buf v out a ? v out a+ v in + v in ? mclk gnd overrange dec_rate av dd 1 av dd 2 av dd 3 av dd 4 dv dd r bias sync reset/pwrdwn v in a+ v in a? fso sco sdi sdo fsi diff multibit - modulator reconstruction decimation fir filter engine ad7765 interface logic and offset and gain correction registers 06519-001 figure 1. the differential input is sampled at up to 40 msps by an analog modulator. the modulator output is processed by a series of low-pass filters. the external clock frequency applied to the ad7765 determines the sample rate, filter corner frequencies, and output word rate. the ad7765 device boasts a full band on-board fir filter. the full stop-band attenuation of the filter is achieved at the nyquist frequency. this feature offers increased protection from signals that lie above the nyquist frequency being aliased back into the input signal bandwidth. the reference voltage supplied to the ad7765 determines the input range. with a 4 v reference, the analog input range is 3.2768 v differential biased around a common mode of 2.048 v. this common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. the ad7765 is available in a 28-lead tssop package and is specified over the industrial temperature range from ?40c to +85c. table 1. relate d de v ices part no. description ad7760 2.5 msps, 100 db, parallel output on-chip buffers ad7762 625 ksps, 109 db, parallel output on-chip buffers ad7763 625 ksps, 109 db, serial output, on-chip buffers ad7764 312 ksps, 109 db, serial output, on-chip buffers ad7766 125 ksps, 108 db, serial output, 20 mw max power ad7767 125 ksps, 108 db, serial output, 20 mw max power
ad7765 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 6 timing diagrams.......................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and functional descriptions.......................... 9 typical performance characteristics ........................................... 11 terminology .................................................................................... 14 theory of operation ...................................................................... 15 - modulation and digital filtering...................................... 15 ad7765 input structure ................................................................ 16 on-chip differential amplifier ............................................... 17 modulator input structure........................................................ 18 ad7765 interface............................................................................ 19 reading data............................................................................... 19 reading status and other registers......................................... 19 writing to the ad7765 .............................................................. 19 ad7765 functionality.................................................................... 20 synchronization.......................................................................... 20 overrange alerts ........................................................................ 20 power modes............................................................................... 20 decimation rate pin.................................................................. 21 daisy chaining ............................................................................... 22 reading data in daisy-chain mode ....................................... 22 writing data in daisy-chain mode ........................................ 23 clocking the ad7765 .................................................................... 24 mclk jitter requirements ....................................................... 24 decoupling and layout information ........................................... 25 supply decoupling ..................................................................... 25 reference voltage filtering ....................................................... 25 differential amplifier components ........................................ 25 layout considerations............................................................... 25 using the ad7765 ...................................................................... 26 bias resistor selection ............................................................... 26 ad7765 registers ........................................................................... 27 control register ......................................................................... 27 status register............................................................................. 27 gain registeraddress 0x0004............................................... 28 overrange registeraddress 0x0005..................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 6/07revision 0: initial version
ad7765 rev. 0 | page 3 of 32 specifications av dd 1 = dv dd = v drive = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, mclk amplitude = 5 v, t a = +25c, normal power mode, using the on-chip amplifier with components as shown in row one of table 7 , unless otherwise noted . 1 table 2 parameter test conditions/comments specification unit dynamic performance decimate 256 normal power mode mclk = 40 mhz, odr = 78.125 khz, f in = 1 khz sine wave dynamic range modulator inputs shorted 115 db typ 110 db min differential amplifier inputs shorted 113.4 db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 db 109 db typ 106 db min spurious-free dynamic range (sfdr) nonharmonic 130 dbfs typ total harmonic distortion (thd) input amplitude = ?0.5 db ?105 db typ input amplitude = ?6 db ?103 db typ input amplitude = ?60 db ?71 db typ low power mode mclk = 40 mhz, odr = 78.125 khz, f in = 1 khz sine wave dynamic range modulator inputs shorted 113 db typ 110 db min differential amplifier inputs shorted 112 db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 db 109 db typ 106 db min total harmonic distortion (thd) inp ut amplitude = ?0.5 db ?105 db typ input amplitude = ?6 db ?111 db typ input amplitude = ?6 db ?100 db max input amplitude = ?60 db ?76 db typ decimate 128 normal power mode mclk = 40 mhz, odr = 156.25 khz, f in = 1 khz sine wave dynamic range modulator inputs shorted 112 db typ 108 db min differential amplifier inputs shorted 110.4 db typ 107 db typ signal to noise ratio (snr) 2 105 db min spurious-free dynamic range (sfdr) nonharmonic 130 dbfs typ input amplitude = ?0.5 db ?105 db typ total harmonic distortion (thd) input amplitude = ?6 db ?103 db typ input amplitude = ?6 db, f in a = 50.3 khz, f in b = 47.3 khz second-order terms ?117 db typ intermodulation distortion (imd) third-order terms ?108 db typ low power mode mclk = 40 mhz, odr = 156.25 khz, f in = 1 khz sine wave 110 db typ modulator inputs shorted 109 db min dynamic range differential amplifier inputs shorted 109 db typ 107 db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 db 105 db min total harmonic distortion (thd) inp ut amplitude = ?0.5 db ?105 db typ input amplitude = ?6 db ?111 db typ input amplitude = ?6 db ?100 db max intermodulation distortion (imd) input amplitude = ?6 db, f in a= 50.3 khz, f in b = 47.3 khz second-order terms ?134 db typ third-order terms ?110 db typ
ad7765 rev. 0 | page 4 of 32 parameter test conditions/comments specification unit dc accuracy resolution guaranteed monotonic to 24 bits 24 bits normal power mode 0.0036 % typ integral nonlinearity low power mode 0.0014 % typ normal power mode 0.006 % typ 0.03 % max including on-chip amplifier 0.04 % typ low power mode 0.002 % typ zero error 0.024 % max 0.018 % typ gain error including on-chip amplifier 0.04 % typ zero error drift 0.00006 %fs/c typ gain error drift 0.00005 %fs/c typ digital filter characteristics pass-band ripple 0.1 db typ pass band 3 ?1 db frequency odr 0.4016 khz ?3db bandwidth 3 odr 0.4096 khz stop band 3 beginning of stop band odr 0.5 khz decimate 128 120 db typ stop-band attenuation decimate 256 115 group delay decimate 128 mclk = 40 mhz 177 s typ decimate 256 mclk = 40 mhz 358 s typ analog input differential input voltage modulator input pins: v in (+) ? v in (?), v ref = 4.096 v 3.2768 v p-p input capacitance at on-chip differential amplifier inputs 5 pf typ at modulator inputs 29 pf typ reference input/output v ref input voltage av dd 3 = 5 v 5% 4.096 v v ref input dc leakage current 1 a max v ref input capacitance 5 pf typ digital input/output mclk input amplitude 2.25 to 5.25 v input capacitance 7.3 pf typ input leakage current 1 a/pin max v inh 0.8 dv dd v min v inl 0.2 dv dd v max v oh 4 2.2 v min v ol 0.1 v max on-chip differential amplifier input impedance >1 m bandwidth for 0.1 db flatness 125 khz common-mode input voltage voltage range at input pins: v in a? and v in a+. ?0.5 to +2.2 v common-mode output voltage on-chip differential amplifier pins: v out + and v out ? 2.048 v power requirements av dd 1 (modulator supply) 5% 2.5 v av dd 2 (general supply) 5% 5 v av dd 3 (differential amplifier supply) 5% 5 v min/max av dd 4 (ref buffer supply) 5% 5 v min/max dv dd 5% 2.5 v
ad7765 rev. 0 | page 5 of 32 parameter test conditions/comments specification unit normal power mode ai dd 1 (modulator) 19 ma typ ai dd 2 (general) 5 mclk = 40 mhz 13 ma typ ai dd 3 (differential amplifier) av dd 3 = 5 v 10 ma typ ai dd 4 (reference buffer) av dd 4 = 5 v 9 ma typ di dd 5 mclk = 40 mhz 37 ma typ low power mode ai dd 1 (modulator) 10 ma typ ai dd 2 (general) 5 mclk = 40 mhz 7 ma typ ai dd 3 (differential amplifier) av dd 3 = 5 v 5.5 ma typ ai dd 4 (reference buffer) av dd 4 = 5 v 5 ma typ di dd 5 mclk = 40 mhz 20 ma typ power dissipation normal power mode 300 mw typ mclk = 40 mhz, decimate 128 371 mw max low power mode mclk = 40 mhz, decimate 128 160 mw typ 215 mw max power-down mode 6 pwrdwn held logic low 1 mw typ 1 see terminology section. 2 snr specifications in decibels are referred to a full-scale input, fs. tested with an input signal at 0.5db below full scale, unless otherwise specified. 3 output data rate (odr) = [(mclk/2)]/decimation rate. that is, the maximum odr for ad7765 = [(40 mhz)/2)/128] = 156.25 khz. 4 tested with a 400 a load current. 5 tested at mclk = 40 mhz. this current scales linearly with mclk frequency applied. 6 tested at 125c.
ad7765 rev. 0 | page 6 of 32 timing specifications av dd 1 = dv dd = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, t a = 25c, c load = 25 pf. table 3. parameter limit at t min , t max unit description f mclk 500 khz min applied master clock frequency 40 mhz max f iclk 250 khz min internal modulator clock derived from mclk 20 mhz max t 1 1 t iclk typ sco high period t 2 1 t iclk typ sco low period t 3 1 ns typ sco rising edge to fso falling edge t 4 2 ns typ data access time, fso falling edge to data active t 5 8 ns max msb data access time, sdo active to sdo valid t 6 40 ns min data hold time (sdo valid to sco rising edge) t 7 9.5 ns max data access time (sco rising edge to sdo valid) t 8 2 ns typ sco rising edge to fso rising edge t 9 32 t sco max fso low period t 10 12 ns min setup time from fsi falling edge to sco falling edge t 11 1 t sco min fsi low period t 12 1 32 t sco max fsi low period t 13 12 ns min sdi setup time for the first data bit t 14 12 ns min sdi setup time t 15 0 ns max sdi hold time 1 this is the maximum time fsi can be held low when writing to an individual device (a device that is not daisy chained).
ad7765 rev. 0 | page 7 of 32 timing diagrams d22 d23 d21 d20 d19 d1 d0 st4 st3 st2 st1 st0 0 0 0 sco (o) fso (o) sdo (o) t 1 t 9 32 t sco t 2 t 8 t 3 t 4 t 5 t 7 t 6 0 6519-002 figure 2. serial read timing diagram ra15 ra14 ra13 ra12 ra11 ra10 ra9 ra8 ra1 ra0 d15 d14 d1 d0 sco (o) fsi (i) sdi (i) t 12 t 1 t 10 t 13 t 14 t 15 t 11 t 2 06519-003 figure 3. ad7765 register write status register contents [31:16] don?t care bits [15:0] sco (o) sdo (o) fsi (i) sdi (i) fso (o) 8 t sco next data read following the write to control register control register addr (0x0001) control register instruction 06519-004 figure 4. ad7765 status register read cycle
ad7765 rev. 0 | page 8 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 4 parameters rating av dd 1 to gnd ?0.3 v to +2.8 v av dd 2, av dd 3, av dd 4 to gnd ?0.3 v to +6 v dv dd to gnd ?0.3 v to +2.8 v v in a+ , v in a? to gnd 1 ?0.3 v to +6 v v in + , v in ? to gnd 1 ?0.3 v to +6 v digital input voltage to gnd 2 ?0.3 v to +2.8 v v ref to gnd 3 ?0.3 v to +6 v agnd to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 4 10 ma operating temperature range commercial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 143c/w jc thermal impedance 45c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv 1 absolute maximum voltage for v in ?, v in +, v in a?, and v in a+ is 6.0 v or av dd 3 + 0.3 v, whichever is lower. 2 absolute maximum voltage on digital inputs is 3.0 v or dv dd + 0.3 v, whichever is lower. 3 absolute maximum voltage on v ref input is 6.0 v or av dd 4 + 0.3 v, whichever is lower. 4 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7765 rev. 0 | page 9 of 32 pin configuration and fu nctional descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v out a+ v in a+ v out a? av dd 2 v in + v in ? v in a? v ref + refgnd av dd 4 r bias agnd1 av dd 1 agnd3 overrange sco fsi sdo fso av dd 2 agnd2 mclk sync sdi reset/pwrdwn dv dd dec_rate av dd 3 ad7765 top view (not to scale) 06519-005 figure 5. 28-lead tssop pin configuration table 5. pin function descriptions pin no. mnemonic description 24 av dd 1 2.5 v power supply for modulator. this pin should be decoupled to agnd1 (pin 23) with a 100 nf capacitor. 7 and 21 av dd 2 5 v power supply. pin 7 should be decoupled to agnd3 (pin 8) with a 100 nf capacitor. pin 21 should be decoupled to agnd1 (pin 23) with a 100 nf capacitor. 28 av dd 3 3.3 v to 5 v power supply for differential amplifier. th is pin should be decoupled to the ground plane with a 100 nf capacitor. 25 av dd 4 3.3 v to 5 v power supply for reference buffer. this pi n should be decoupled to agnd1 (pin 23) with a 100 nf capacitor. 17 dv dd 2.5 v power supply for digital circuitry and fir filter. th is pin should be decoupled to the ground plane with a 100 nf capacitor. 22 r bias bias current setting pin. a resistor must be inserted between this pin and agnd. for more details, see the bias resistor selection section. 23 agnd1 power supply ground for analog circuitry. 20 agnd2 power supply ground for analog circuitry. 8 agnd3 power supply ground for analog circuitry. 26 refgnd reference ground. ground connection for the reference voltage. 27 v ref + reference input. 1 v in a? negative input to differential amplifier. 2 v out a+ positive output from differential amplifier. 3 v in a+ positive input to differential amplifier. 4 v out a? negative output from differential amplifier. 5 v in ? negative input to the modulator. 6 v in + positive input to the modulator. 9 overrange overrange pin. this pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 sco serial clock out. this clock signal is derived from the in ternal iclk signal. the freque ncy of this clock is equal to iclk. see the clocking the ad7765 section for further details. 11 fso frame sync out. this signal frames the se rial data output and is 32 sco periods wide. 12 sdo serial data out. data and status are o utput on this pin during ea ch serial transfer. each bit is clocked out on an sco rising edge and is valid on the falling edge. see the ad7765 interface section for further details. 13 sdi serial data in. the first data bit (msb) must be valid on the next sco falling edge after the fsi event is latched. 32 bits are required for each write; the first 16-bit wo rd contains the device and register address and the second word contains the data. see the ad7765 interface section for further details.
ad7765 rev. 0 | page 10 of 32 pin no. mnemonic description 14 fsi frame sync input. the status of this pin is checked on the falling edge of sco. if this pin is low, then the first data bit is latched in on the next sco falling edge. see the ad7765 interface section for further details. 15 sync synchronization input. a falling edge on this pin resets the internal filt er. this can be used to synchronize multiple devices in a system. see the synchronization section for further details. 16 reset / pwrdwn reset/powerdown pin. when a logic low is sensed on th is pin, the part is powered down and all internal circuitry is reset. 19 mclk master clock input. a low jitter digital clock must be ap plied to this pin. the output data rate depends on the frequency of this clock. see the clocking the ad7765 section for more details. 18 dec_rate decimation rate. this pin selects one of the three decimation rate modes. when 2.5 v is applied to this pin, a decimation rate of 128 is selected. a decimation rate of 256 is selected by setting the pin to ground.
ad7765 rev. 0 | page 11 of 32 typical performance characteristics av dd 1 = dv dd = v drive = 2.5 v, av dd 2 = av dd 3 = av dd 4 = 5 v, v ref + = 4.096 v, mclk amplitude = 5 v, t a = 25c. linearity plots are measured to 16-bit accuracy. the input signal is reduced to avoid modulator overload and digital clipping. fast fourier transfo rms (ftts) of ?0.5 db tones are generated from 262,144 samples in normal power mode. all other ffts are generated from 8,192 samples. 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 20k 40k 60k 78.124k amplitude (db) frequency (hz) 06519-007 0 10k 20k 30k 40k 50k 60k 70k amplitude (db) frequency (hz) 06519-211 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 6. normal power mode; fft,1 khz, ?0.5 db input tone, 128 decimation rate figure 9. low power mode; fft,1 khz, ?0.5 db input tone, 128 decimation rate 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 10k 20k 30k 39.062k amplitude (db) frequency (hz) 06519-008 0 5k 10k 15k 20k 25k 30k 35k amplitude (db) frequency (hz) 06519-210 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 10. low power mode; fft,1 khz, ?0.5 db input tone, 256 decimation rate figure 7. normal power mode; fft,1 khz, ?0.5 db input tone, 256 decimation rate 0 50k 75k 25k amplitude (db) frequency (hz) 06519-204 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 50k 75k 25k amplitude (db) frequency (hz) 06519-201 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 8. normal power mode; fft,1 khz, ?6 db input tone, 128 decimation rate figure 11. low power mode; fft,1 khz, ? db input tone, 128 decimation rate
ad7765 rev. 0 | page 12 of 32 0 50k 75k 25k amplitude (db) frequency (hz) 06519-201 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 0 35k 30k 25k 20k 15k 10k 5k amplitude (db) frequency (hz) 06519-205 0 ?25 ?50 ?75 ?100 ?125 ?150 ?175 figure 12. normal power mode; fft,1 khz, ?6 db input tone, 256 decimation rate figure 15 low power mode; fft,1 khz, ?6 db input tone, 256 decimation rate 25 20 15 10 5 0 0 1 02 03 0 4 40 5 1 52 53 5 current (ma) mclk frequency (mhz) dv dd 40 35 30 25 20 15 10 5 0 0 1 02 03 0 4 40 5 1 52 53 5 current (ma) mclk frequency (mhz) dv dd 5 av dd 2 av dd 3 av dd 4 av dd 1 06519-114 5 av dd 2 av dd 4 av dd 1 av dd 3 06519-115 figure 16. low power mode; current consumption vs. mclk frequency, 128 decimation rate figure 13. normal power mode; curren t consumption vs. mclk frequency, 128 decimation rate 20 18 16 14 12 10 8 6 4 2 0 0 1 02 03 04 5 1 52 53 5 current (ma) mclk frequency (mhz) dv dd 40 35 30 25 20 15 10 5 0 0 1 02 03 04 5 1 52 53 5 current (ma) mclk frequency (mhz) av dd 1 dv dd 0 av dd 2 av dd 3 av dd 4 06519-112 0 av dd 2 av dd 3 av dd 4 av dd 1 06519-113 figure 14. normal power mode; curren t consumption vs. mclk frequency, 256 decimation rate figure 17. low power mode; current consumption vs. mclk frequency, 256 decimation rate
ad7765 rev. 0 | page 13 of 32 6k 55k 59535 10k 15k 20k 25k 30k 35k 40k 45k 50k inl (%) 16-bit code scaling ?40c +25c +85c 06519-207 0.003225 0.003000 0.002250 0.001500 0.000075 0 ?0.000120 0.00300 ?0.00300 ?0.00225 ?0.00150 ?0.00075 0 0.00075 0.00150 0.00225 6k 55k 59535 10k 15k 20k 25k 30k 35k 40k 45k 50k inl (%) 16-bit code scaling ?40c +25c +85c 06519-206 figure 18. normal power mode inl figure 21. low power mode inl 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 78124 60k 40k 20k amplitude (db) frequency (hz) 06519-209 06519-009 110 109 108 107 106 105 104 103 102 0 64 128 192 256 low snr snr (db) decimation rate normal snr figure 19. normal power mode; imd, f in a = 49.7 khz, f in b = 50.3 khz, 50 khz center frequency, 128 decimation rate figure 22. normal and low power mode; snr vs. decimation rate, 1 khz, ?0.5 db input tone 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 6k 55k 59535 10k 15k 20k 25k 30k 35k 40k 45k 50k dnl (lsb) code 06519-208 figure 20. dnl plot
ad7765 rev. 0 | page 14 of 32 terminology signal-to-noise ratio (snr) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist fre- quency, excluding harmonics and dc. the value for snr is expressed in decibels (db). zero error drift the change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. gain error the first transition (from 100000 to 100001) should occur for an analog voltage 1/2 lsb above the nominal negative full scale. the last transition (from 011110 to 011111) should occur for an analog voltage 1 1/2 lsb below the nominal full scale. the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the ad7765, it is defined as () 1 6 54 32 v vvvvv thd 22222 log20db ++++ = where: gain error drift the change in the actual gain error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. nonharmonic spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. dynamic range the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in db. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second- order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7765 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, that is, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in db. integral nonlinearity (inl) the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero error the difference between the ideal midscale input voltage (when both inputs are shorted together) and the actual voltage producing the midscale output code.
ad7765 rev. 0 | page 15 of 32 theory of operation the ad7765 employs three fir filters in series. by using different combinations of decimation ratios, data can be obtained from the ad7765 at three data rates. the ad7765 features an on-chip fully differential amplifier to feed the - modulator pins , an on-chip reference buffer, and a fir filter block to perform the required digital filtering of the - modulator output. using this - conversion technique with the added digital filtering, the analog input is converted into an equivalent digital word. the first filter receives data from the modulator at iclk mhz where it is decimated 4 to output data at (iclk/4) mhz . the second filter allows a choice of decimation rates: 16 or 32. - modulation and digital filtering the digital filtering on the ad7765 provides full-band filtering. this means that its stop-band attenuation occurs at the nyquist frequency (odr/2). this feature provides increased protection against aliasing of sampled frequencies that lie above the nyquist rate (odr/2). the filter gives maximum attenuation at the nyquist rate (see the input waveform applied to the modulator is sampled and an equivalent digital word is output to the digital filter at a rate equal to iclk. by employing oversampling, the quantization noise is spread across a wide bandwidth from 0 to f iclk , this means that the noise energy contained in the signal band of interest is reduced (see figure 26 ). this means that it attenuates all possible alias frequencies by 115 db or greater. the frequency response in figure 23 ). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see figure 26 occurs when the ad7765 is operated with a 40 mhz mclk in the decimate 128 mode. note that the first stop-band frequency occurs at nyquist. the frequency response of the filter scales with both the decimation rate chosen and the mclk frequency applied. figure 24 ). quantization noise f iclk /2 band of interest 06519-012 the third filter has a fixed decimation rate of 2. table 6 shows some characteristics of the digital filtering where iclk = mclk /2. the group delay of the filter is defined to be the delay to the center of the impulse response and is equal to the computation plus the filter delays. the delay until valid data is available (the filter-settle status bit is set) is approximately twice the filter delay plus the computation delay. this is listed in terms of mclk periods in figure 23. - adc, quantization noise f iclk /2 noise shaping band of interest 06519-013 tabl e 6 . 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 03 250 200 150 100 50 amplitude (db) frequency (khz) 0 0 pass-band ripple = 0.05db ?0.1db frequency = 125.1khz ?3db frequency = 128khz stop band = 156.25khz 06519-015 figure 24. - adc, noise shaping f iclk /2 band of interest digital filter cutoff frequency 06519-014 figure 25. - adc, digita l filter cutoff frequency the digital filtering that follows the modulator removes the large out-of-band quantization noise (see figure 25 ) while also reducing the data rate from f iclk at the input of the filter to f iclk /128 or less at the output of the filter, depending on the decimation rate used. figure 26. filter frequency response (156.25 khz odr) table 6. configuration with default filter sync iclk frequency decimation rate data state computation delay filter delay to filter-settle pass-band bandwidth output data rate (odr) 20 mhz 128 fully filtered 3.1 s 174 s 14217 x t mclk 62.5 khz 156.25 khz 20 mhz 256 fully filtered 4.65 s 346.8 s 27895 x t mclk 31.25 khz 78.125 khz 12.288 mhz 128 fully filtered 5.05 s 283.2 s 14217 x t mclk 38.4 khz 96 khz 12.288 mhz 256 fully filtered 7.57 s 564.5 s 27895 x t mclk 19.2 khz 48 khz
ad7765 rev. 0 | page 16 of 32 ad7765 input structure v5536.68.0v192.8 _ = = fullscale input modulator the ad7765 requires a 4.096 v input to the reference pin v ref +, supplied by a high precision reference, such as the adr444. because the input to the devices - modulator is fully differential, the effective differential reference range is 8.192 v. this means that a maximum of 3.2768 v p-p can be applied to each of the ad7765 modulator inputs (pin 5 and pin 6), with the ad7765 being specified with an input ?0.5 db down from full scale (?0.5 dbfs). v v diffref 192.8096.42 )( == + the ad7765 modulator inputs must have a common-mode input of 2.048 v. figure 27 shows the relative scaling between the differential voltages applied to the modulator pins and the respective 24-bit twos complement digital outputs. as is inherent in - modulators, only a certain portion of this full reference may be used. in the case of the ad7765, 80% of the full differential reference can be applied to the modulators differential inputs. input to modulator pin 5 and pin 6 v in ? and v in + v in + = 3.6855v 0111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 +3.2768v = modulator full-scale = 80% of 4.096v 80% of 4.096v = modulator full-scale = ?3.2768v +4.096v ?4.096v v in ? = 0.4105v v in + = 2.048v v in ? = 2.048v v in ? = 3.6855v v in + = 0.4105v 1000 0000 0000 0000 0000 0000 0111 1000 1101 0110 1111 1101 1000 0111 0010 1001 0000 0010 ?0.5dbfs input ?0.5dbfs input overrange region overrange region digital output on sdo pin 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 twos complement digital output input voltage (v) 0 6519-120 figure 27. ad7765 scaling; modulator input voltage vs. digital output code
ad7765 rev. 0 | page 17 of 32 the common-mode input at each of the differential amplifier inputs (pin v in a and pin v in a?) can range from?0.5 v dc to 2.2 v dc. the amplifier has a constant output common-mode voltage of 2.048 v, that is, v ref /2, the requisite common-mode voltage for the modulator input pins (v in + and v in ?). on-chip differential amplifier the ad7765 contains an on-board differential amplifier that is recommended to drive the modulator input pins. pin 1, pin 2, pin 3, and pin 4 on the ad7765 are the differential input and output pins of the amplifier. the external components, r in , r fb , c fb , c s , and r m , are placed around pin 1 through pin 6 to create the recommended configuration. to achieve the specified performance, the differential amplifier should be configured as a first-order antialias filter, as shown in figure 29 shows the signal conditioning that occurs using the differential amplifier configuration detailed in table 7 with a 2.5 v input signal to the differential amplifier. the amplifier in this example is biased around ground and is scaled to give 3.168 v p-p (?0.5 dbfs) on each modulator input with a 2.048 v common mode. figure 28 using the component values listed in table 7 . the inputs to the differential amplifier are then routed through this external component network before being applied to the modulator inputs v in ? and v in +(pin 5 and pin 6). using the optimal values in the table as an example yields a 25 db attenuation at the first alias point of 19.84 mhz. 0v +2.5v ?2.5v 0v +2.5v ?2.5v a b +3.632v +2.048v +0.464v +3.632v +2.048v +0.464v v in + v in ? 06519-122 diff amp r in r fb c fb r in r m r m c s c m r fb c fb v in ? a b v in + 0 6519-024 1 3 2 4 5 6 v in a? v in a+ v out a+ v out a? figure 29. differential amplifier signal conditioning to obtain maximum performance from the ad7765, it is advisable to drive the adc with differential signals. figure 28. differential amplifier configuration figure 30 shows how a bipolar, single-ended signal biased around ground can drive the ad7765 with the use of an external op amp, such as the ad8021. table 7. on-chip differential filter component values r in (k) r fb (k) r m () c s (pf) c fb (pf) c m (pf) diff amp r in r fb c fb r in r m r m c s r fb c fb v in ? v in v in + ad8021 2r 2r r c m 0 6519-026 optimal 4.75 3.01 43 8.2 47 33 tolerance range 1 2.37 to 5.76 2.4 to 4.87 36 to 47 0 to 10 20 to 100 39 to 56 1 values shown were the acceptable tolerances for each component when altered relative to the optimal va lues used to achieve the stated specifications of the device. the range of values that can be used for each of the listed components in the differential amplifier configuration is also listed in table 7 . when using the differential amplifier to gain the input voltages to the required modulator input range, it is advisable to implement the gain function by changing r in , leaving the r fb as the listed optimal value. figure 30. single-ended-t o-differential conversion
ad7765 rev. 0 | page 18 of 32 modulator input structure sampling switches ss1 and ss3 are driven by iclk, whereas sampling switches ss2 and ss4 are driven by iclk the ad7765 employs a double-sampling front end, as shown in . when iclk is high, the analog input voltage is connected to cs1. on the falling edge of iclk, the ss1 and ss3 switches open and the analog input is sampled on cs1. similarly, when iclk is low, the analog input voltage is connected to cs2. on the rising edge of iclk, the ss2 and ss4 switches open, and the analog input is sampled on cs2. figure 31 . for simplicity, only the equivalent input circuitry for v in + is shown. the equivalent circuitry for v in ? is the same. cs2 cpb2 ss4 sh4 cpa ss2 sh2 cs1 cpb1 ss3 sh3 ss1 sh1 analog modulator v in + 06519-027 capacitors cpa, cpb1, and cpb2 represent parasitic capaci- tances that include the junction capacitances associated with the mos switches. table 8. equivalent component values cs1 cs2 cpa cpb1/2 13 pf 13 pf 13 pf 5 pf figure 31. equivalent input circuit
ad7765 rev. 0 | page 19 of 32 ad7765 interface reading data the ad7765 uses an spi-compatible serial interface. the timing diagram in figure 2 shows how the ad7765 transmits its conversion results. the data read from the ad7765 is clocked out using the serial clock output (sco). the sco frequency is half that of the mclk input to the ad7765. the conversion result output on the serial data output (sdo) line is framed by the frame synchronization output, fso , which is sent logic low for 32 sco cycles. each bit of the new conversion result is clocked onto the sdo line on the rising sco edge and is valid on the falling sco edge. the 32-bit result consists of the 24 data bits followed by five status bits followed further by three zeros. the five status bits are listed in table 9 and described below the table. table 9. status bits during data read d7 d6 d5 d4 d3 filter-settle ovr lpwr dec_rate 1 dont care ? the filter-settle bit indicates whether the data output from the ad7765 is valid. after resetting the device (using the reset pin) or clearing the digital filter (using the sync pin), the filter-settle bit goes logic low to indicate that the full settling time of the filter has not yet passed and that the data is not yet valid. the filter- settle bit also goes to zero when the input to the part has asserted the overrange alerts. ? the ovr (overrange) bit is described in the overrange alerts section. ? the lpwr bit is set to logic high when the ad7765 is operating in low power mode. see the power modes section for further details. ? the dec_rate 1 and dec_rate 0 bits indicate the decimation ratio used. table 10 is a truth table for the decimation rate bits. table 10. truth table decimate dec_rate 1 128 1 256 0 reading status and other registers the ad7765 features a gain correction register, an overrange register, and a read-only status register. to read back the contents of these registers, the user must first write to the control register of the device and set the bit that corresponds to the register to be read. the next read operation outputs the contents of the selected register (on the sdo pin) instead of a conversion result. to ensure that the next read cycle contains the contents of the register written to, the write operation to that register must be completed a minimum of 8 t sco before the falling edge of fso , which indicates the start of the next read cycle. see figure 4 for further details. the ad7765 registers section provides more information on the relevant bits in the control register. writing to the ad7765 a write operation to the ad7765 is shown in figure 3 . the serial writing operation is synchronous to the sco signal. the status of the frame synchronization input, fsi , is checked on the falling edge of the sco signal. if the fsi line is low, then the first data bit on the serial data in (sdi) line is latched in on the next sco falling edge. set the active edge of the fsi signal to occur at a position when the sco signal is high or low to allow setup and hold times from the sco falling edge to be met. the width of the fsi signal can be set to between 1 and 32 sco periods wide. a second, or subsequent, falling edge that occurs before 32 sco periods have elapsed, is ignored. figure 3 details the format for the serial data being written to the ad7765 through the sdi pin. thirty-two bits are required for a write operation. the first 16 bits are used to select the register address for which the data being read is intended. the second 16 bits contain the data for the selected register. writing to the ad7765 is allowed at any time, even while reading a conversion result. note that after writing to the devices, valid data is not output until after the settling time for the filter has elapsed. the filter-settle status bit is asserted at this point to indicate that the filter has settled and that valid data is available at the output.
ad7765 rev. 0 | page 20 of 32 ad7765 functionality synchronization sync the input to the ad7765 provides a synchronization function that allows the user to begin gathering samples of the analog front-end input from a known point in time. the sync function allows multiple ad7765 devices, operated from the same master clock that use common sync and reset signals to be synchronized so that each adc simultaneously updates its output register. connect common mclk, sync , and reset signals to all ad7765 devices in the system. on the falling edge of the sync signal, the digital filter sequencer is reset to 0. the filter is held in a reset state until a rising edge of the sco senses sync high. thus, to perform a synchronization of devices, a sync pulse of a minimum of 2.5 iclk cycles in length can be applied, synchronous to the falling edge of sco. on the first rising edge of sco after sync goes logic high, the filter is taken out of reset, and the multiple parts gather input samples synchronously. following a sync , the digital filter needs time to settle before valid data can be read from the ad7765. the user knows there is valid data on the sdo line by checking the filter-settle status bit (see d7 in table 9 ) that is output with each conversion result. the time from the rising edge of sync until the filter- settle bit asserts depends on the filter configuration used. see the theory of operation section and the values listed in table 6 for details on calculating the time until filter- settle asserts. note that the filter-settle bit is designed as a reactionary flag to alert the user when the conversion data output is valid. overrange alerts the ad7765 offers an overrange function in both a pin and status bit output. the overrange alerts indicate when the voltage applied to the ad7765 modulator input pins exceeds the limit set in the overrange register, indicating that the voltage applied is approaching an overrange level for the modulator. to set this limit, the user must program the register. the default overrange limit is set to 80% of the v ref voltage (see the ad7765 registers section). the overrange pin outputs logic high to alert the user that the modulator has sampled an input voltage greater in magnitude than the overrange limit as set in the overrange register. the overrange pin is set to logic high when the modulator samples an input above the overrange limit. once the input returns below the limit, the overrange pin returns to zero. the overrange pin is updated after the first fir filter stage. its output changes at the iclk/4 frequency. the ovr status bit is output as bit d6 on sdo during a data conversion and can be checked in the ad7765 status register. this bit is less dynamic than the overrange pin output. it is updated on each conversion result output, that is, the bit changes at the output data rate. if the modulator has sampled a voltage input that exceeded the overrange limit during the process of gathering samples for a particular conversion result output, then the ovr bit is set to logic high. overrange pin output logi c level hi lo ovr bit logic level hi lo output frequency of fir filter 1 = iclk/4 overrange limit overrange limit obsolute input to ad7765 [(v in +) ? (v in ?)] output data rate (odr) (iclk/decimation rate t t 06519-016 figure 32. overrange pin and ov r bit vs. absolute voltage applied to modulator the output points from fir filter 1 in figure 32 are not drawn to scale relative to the output data rate points. the fir filter 1 output is updated either 16 or 32 faster than the output data rate depending on the decimation rate in operation. power modes during power-up, the ad7765 defaults to operate in normal power mode. there is no register write required. the ad7765 also offers low power mode. to operate the device in low power mode, the user sets the lpwr bit in the control register to logic high (see figure 33 ). operating the ad7765 in low power mode has no impact on the output data rate or available bandwidth. sco (o) control register address 0x0001 low power mode data 0x0010 fsi (i) sdi (i) 32 t sco 0 6519-017 figure 33. write scheme for low power mode the ad7765 features a reset pwrdwn / pin. holding the input to this pin logic low places the ad7765 in power-down mode. all internal circuitry is reset. to utilize the reset functionality, pulse the input to this pin low for a minimum of one mclk period. this action resets the internal circuitry. when the ad7765 receives a logic high input on the reset / pwrdwn pin, the device powers up.
ad7765 rev. 0 | page 21 of 32 decimation rate pin the decimation rate of the ad7765 is selected using the dec_rate pin. table 11 shows the voltage input settings required for each of the three decimation rates. table 11. dec_rate pin settings decimate dec_rate pin max output data rate 128 dvdd 156.25 khz 256 gnd 78.125 khz
ad7765 rev. 0 | page 22 of 32 daisy chaining daisy chaining devices allows numerous devices to use the same digital interface lines. this feature is especially useful for reducing component count and wiring connections, such as in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. the block diagram in figure 34 shows how to connect devices to achieve daisy-chain functionality. figure 34 shows four ad7765 devices daisy-chained together with a common mclk signal applied. reading data in daisy-chain mode referring to figure 34 , note that the sdo line of ad7765 (a) provides the output data from the chain of ad7765 converters. also, note that for the last device in the chain, ad7765 (d), the sdi pin is connected to ground. all of the devices in the chain must use common mclk and sync signals. to enable the daisy-chain conversion process, apply a common sync pulse to all devices (see the synchronization section). after applying a sync pulse to all devices, the filter settling time must pass before the filter-settle bit is asserted indicating valid conversion data at the output of the chain of devices. as shown in figure 35 , the first conversion result is output from the device labeled ad7765 (a). this 32-bit conversion result is then followed by the conversion results from the devices ad7765 (b), ad7765 (c), and ad7765 (d), respectively with all conversion results output in an msb first sequence. the signals output from the daisy chain are the stream of conversion results from the sdo pin of ad7765 (a) and the fso signal output by the first device in the chain, ad7765 (a). the falling edge of fso signals the msb of the first conversion output in the chain. fso stays logic low throughout the 32 sco clock periods needed to output the ad7765 (a) result and then goes logic high during the output of the conversion results from the devices ad7765 (b), ad7765 (c), and ad7765 (d). the maximum number of devices that can be daisy-chained is dependent on the decimation rate selected. calculate the maximum number of devices that can be daisy chained by simply dividing the chosen decimation rate by 32 (the number of bits that must be clocked out for each conversion). table 12 provides the maximum number of chained devices for each decimation rate. table 12. maximum chain length for all decimation rates decimation rate maximum chain length 256 8 128 4 sync sdi fsi sdo mclk ad7765 (d) fsi sync mclk sync sdi fsi sdo mclk ad7765 (c) sync sdi fsi sdo mclk ad7765 (b) sync sdi fsi mclk ad7765 (a) sdo fso 06519-018 figure 34. daisy-chaining four devices in decimate 128 mode using a 40 mhz mclk signal sco fso (a) 32 t sco 32 t sco 32 t sco 32 t sco sdo (a) ad7765 (a) 32-bit output ad7765 (b) 32-bit output ad7765 (c) 32-bit output ad7765 (d) 32-bit output ad7765 (a) 32-bit output ad7765 (b) 32-bit output sdi (a) = sdo (b) ad7765 (b) ad7765 (c) ad7765 (d) ad7765 (b) ad7765 (c) sdi (b) = sdo (c) ad7765 (c) ad7765 (d) ad7765 (c) ad7765 (d) sdi (c) = sdo (d) ad7765 (d) ad7765 (d) 06519-019 figure 35. daisy-chain mode, data read timing diagram (for daisy-chain configuration shown in figure 34 )
ad7765 rev. 0 | page 23 of 32 writing data in daisy-chain mode writing to ad7765 devices in daisy-chain mode is similar to writing to a single device. the serial writing operation is synchronous to the sco signal. the status of the frame synchro- nization input, fsi , is checked on the falling edge of the sco signal. if the fsi line is low, then the first data bit on the serial data in the sdi line is latched in on the next sco falling edge. writing data to the ad7765 in daisy-chain mode operates with the same timing structure as writing to a single device (see figure 3 ). the difference between writing to a single device and writing to a number of daisy-chained devices is in the implementation of the fsi signal. the number of devices that are in the daisy chain determines the period for which the fsi signal must remain logic low. to write to n number of devices in the daisy chain, the period between the falling edge of fsi and the rising edge of fsi must be between 32 (n?1) to 32 n sco periods. for example, if three ad7765 devices are being written to in daisy-chain mode, fsi is logic low for between 32 (3?1) to 32 3 sco pulses. this means that the rising edge of fsi must occur between the 64 th and 96 th sco period. the ad7765 devices can be written to at any time. the falling edge of fsi overrides all attempts to read data from the sdo pin. in the case of a daisy chain, the fsi signal remaining logic low for more than 32 sco periods indicates to the ad7765 device that there are more devices further on in the chain. this means the ad7765 directs data that is input on the sdi pin to its sdo pin. this ensures that data is passed to the next device in the chain, sync sdi fsi sdo mclk ad7765 (d) fsi sync mclk sync sdi fsi sdo mclk ad7765 (c) sync sdi fsi sdo mclk ad7765 (b) sync sdi fsi mclk ad7765 (a) sdo fso sdi 06519-020 figure 36. writing to ad7765 daisy-chain configuration fsi sco sdi (d) sdi (c) = sdo (d) sdi (b) = sdo (c) sdi (a) = sdo (b) sdi (d) sdi (c) sdi (b) sdi (a) 32 t sco 32 t sco 32 t sco 31 t sco t 10 06519-021 figure 37. daisy-chain write timing diagram. writing to four ad7765 devices
ad7765 rev. 0 | page 24 of 32 clocking the ad7765 the ad7765 requires an external low jitter clock source. this signal is applied to the mclk pin. an internal clock signal (iclk) is derived from the mclk input signal. the iclk controls the internal operation of the ad7765. the maximum iclk frequency is 20 mhz. to gener ate t he ic lk ps470 10102.192 256 45.53 )( = = rmsj t the input amplitude also has an effect on these jitter figures. for example, if the input level is 3 db below full-scale, the allowable jitter is increased by a factor of 2, increasing the first example to 57.75 ps rms. this happens when the maximum slew rate is decreased by a reduction in amplitude. iclk = mclk /2 for output data rates equal to those used in audio systems, a 12.288 mhz iclk frequency can be used. as shown in table 6 , output data rates of 96 khz and 48 khz are achievable with this iclk frequency. figure 38 and figure 39 illustrate this point, showing the maximum slew rate of a sine wave of the same frequency, but with different amplitudes. mclk jitter requirements 1.0 ?1.0 0.5 0 ?0.5 06519-022 the mclk jitter requirements depend on a number of factors and are given by 20 )( 10 2 )( dbsnr f osr t in rms j = where: osr = oversampling ratio = f iclk /odr . f in = maximum input frequency. snr(db) = target snr. example 1 this example can be taken from table 6 , where: odr = 156.25 khz. f iclk = 20 mhz. f in (max) = 78.625 khz. snr = 104 db. figure 38. maximum slew rate of sine wave with amplitude of 2 v p-p 1.0 ?1.0 0.5 0 ?0.5 06519-023 ps t rmsj 29.102 1010625.782 128 35.53 )( = = this is the maximum allowable clock jitter for a full-scale, 78.625 khz input tone with the given iclk and output data rate. example 2 ta ke a s e cond e x ample for tabl e 6 , where: odr = 48 khz. f iclk = 12.288 mhz. f in (max) = 19.2 khz. snr = 109 db. figure 39. maximum slew rate of same frequency sine wave with amplitude of 1 v p-p
ad7765 rev. 0 | page 25 of 32 decoupling and layout information 7 .5v vout 2 +vin 6 4 10f 100nf + 100nf + adr444 gnd v ref + pin 27 100f 200 ? 06519-134 supply decoupling the decoupling of the supplies applied to the ad7765 is important in achieving maximum performance. each supply pin must be decoupled to the correct ground pin with a 100 nf, 0603 case size capacitor. figure 41. reference connection pay particular attention to decoupling pin 7 (av dd 2) directly to the nearest ground pin (pin 8). the digital ground pin, agnd2 (pin 20) is routed directly to ground. also, connect refgnd (pin 26) directly to ground. differential amplifier components the correct components for use around the on-chip differential amplifier are detailed in table 7 . matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier. a tolerance of 0.1% or better is required for these components. symmetrical routing of the tracks on both sides of the differential amplifier also assists in achieving stated performance. the dv dd (pin 17) and av dd 3 (pin 28) supplies should be decoupled to the ground plane at a point away from the device. it is advised to decouple the supplies that are connected to the following supply pins through 0603 size,100nf capacitors to a star ground point linked to pin 23 (agnd1) figure 42 shows a typical layout for the components around the differential amplifier. note that the traces for both differential paths are made as symmetrical as possible, and the feedback resistors and capacitors are placed on the underside of the pcb to enable the simplest routing. ? v ref + (pin 27) ? av dd 4 (pin 25) ? av dd 1 (pin 24) ? av dd 2 (pin 21) r fb c fb r in r in v in a? v in a+ 06519-135 a layout decoupling scheme for the these supplies, which connect to the right hand side of the ad776, is shown in figure 40 . note the star-point ground created at pin 23. av dd 2 (pin 21) v ref + (pin 27) gnd pin 23 s tar-point gnd av dd 4 (pin 25) av dd 3 (pin 28) via to gnd from pin 20 av dd 1 (pin 24) gnd pin 15 06519-133 figure 42.typical layout structure for surrounding components layout considerations while using the correct components is essential to achieving optimum performance, the correct layout is just as important. the ad7765 product page on analog.com contains the gerber files for the ad7765 evaluation board. these files should be downloaded and used as a reference when designing any system using the ad7765. figure 40.ad7765 supply decoupling reference voltage filtering the use of ground planes should also be carefully considered. to ensure that the return currents through the decoupling capacitors are flowing to the correct ground pin, the ground side of the capacitors should be as close to the ground pin associated with that supply as recommended in the a low noise reference source, such as the adr444 or adr34 (4.096 v), is suitable for use with the ad7765. the reference voltage supplied to the ad7765 should be decoupled and filtered, as shown in figure 41 . supply decoupling the recommended scheme for the reference voltage supply is a 200 series resistor connected to a 100 f tantalum capacitor, followed by a 10 nf decoupling capacitor very close to the v ref + pin section.
ad7765 rev. 0 | page 26 of 32 using the ad7765 the following is the recommended sequence for powering up and using the ad7765: 1. apply power to the device. 2. start the clock oscillator while applying mclk. 3. ta ke reset low for a minimum of one mclk cycle. 4. wait a minimum of two mclk cycles after reset has been released. 5. if multiple parts are being synchronized, a sync pulse must be applied to the parts. otherwise, no sync pulse is required. when applying the sync pulse ? the issue of a sync pulse to the device must not coincide with a write to the device. ? ensure that the sync pulse is taken low for a minimum of 2.5 iclk cycles. data can then be read from the device using the default gain and overrange threshold values. the conversion data read is not valid, however, until the settling time of the filter has elapsed. once this has occurred, the filter-settle status bit is set, indicating that the data is valid. values for gain and overrange thresholds can be written to or read from the respective registers at this stage. bias resistor selection the ad7765 requires a resistor to be connected between the r bias and agnd pins. the resistor value should be selected to give a current of 25 a through the resistor to ground. for a 4.096 v reference voltage, the correct resistor value is 160 k.
ad7765 rev. 0 | page 27 of 32 ad7765 registers the ad7765 has a number of user-programmable registers. the control register is used to set the functionality of the on-chip bu ffer and differential amplifier and provides an option to power down the ad7765. there are also digital gain and overrange threshold reg isters. writing to these registers involves writing the register address followed by a 16-bit data word. the register addresses, detail s of individual bits, and default values are provided in this section. control register table 13. control register (address 0x0001, default value 0x0000) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 rd ovr rd gain 0 rd stat 0 sync 0 bypass ref 0 0 0 pwr down lpwr ref buf off amp off table 14. bit descriptions of control register bit mnemonic comment 14 rd ovr 1 , 2 , read overrange. if this bit is set, the next read operat ion outputs the contents of th e overrange threshold register instead of a conversion result. 13 rd gain 1 , 2 read gain. if this bit is set, the next read operati on outputs the contents of the digital gain register. 11 rd stat 1 , 2 read status. if this bit is set, the next read ope ration outputs the contents of the status register. 9 sync 1 synchronize. setting this bit initiates an internal synchron ization routine. setting this bit simultaneously on multiple devices synchronizes all filters. 7 bypass ref bypass reference. setting this bit bypasses the reference buffer if the buffer is off. 3 pwr down power down. a logic high powers the device down witho ut resetting. writing a 0 to this bit powers the device back up . 2 lpwr low power mode. set to logic 1 when ad7765 is in low power mode. 1 ref buf off reference buffer off. asserting this bit powers down the reference buffer. 0 amp off amplifier off. asserting this bit switches the differential amplifier off. 1 bit 14 to bit 11 and bit 9 are self-clearing bits. 2 only one of the bits can be set in any write operation because it determines the contents of the next read operation. status register table 15. status register (read only) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 partno 1 0 0 0 filter- settle 0 ovr 0 1 0 ref buf on amp on lpwr dec 1 dec 0 table 16. bit descriptio ns of status register bit mnemonic comment 15 partno part number. this bit is set to one for the ad7765. 10 filter- settle filter settling bit. this bit corresponds to the filter-settle bit in the status word output in the second 16-bit read operation. it indicates when data is valid. 9 0 zero. this bit is set to logic 0. 8 ovr overrange. if the current analog input exceeds the current overrange threshold, this bit is set. 4 ref buf on reference buffer on. this bit is set when the reference buffer is in use. 3 amp on amplifier on. this bit is set when the input amplifier is in use. 2 lpwr low power mode. this bit is set when operating in low power mode. 1 to 0 dec[1:0] decimation rate. these bits correspond to decimation rate in use.
ad7765 rev. 0 | page 28 of 32 gain registeraddress 0x0004 non-bit-mapped, default value 0xa000 the gain register is scaled such that 0x8000 corresponds to a gain of 1.0. the default value of this register is 1.25 (0xa000). this results in a full-scale digital output when the input is at 80% of v ref , tying in with the maximum analog input range of 80% of v ref p-p. overrange registeraddress 0x0005 non-bit-mapped, default value 0xcccc the overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. this is prior to any gain scaling or offset adjustment. the default value is 0xcccc, which corre- sponds to 80% of v ref (the maximum permitted analog input voltage). assuming v ref = 4.096 v, the bit is then set when the input voltage exceeds approximately 6.55 v p-p differential. the overrange bit is set immediately if the analog input voltage exceeds 100% of v ref for more than four consecutive samples at the modulator rate.
ad7765 rev. 0 | page 29 of 32 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 43. 28-lead thin shrink small outline [tssop] ( ru-28) dimensions shown in millimeters ordering guide model temperature range package description package option ad7765bruz 1 C40c to +85c 28-lead thin shrink small outline [tssop] ru-28 ad7765bruz-reel7 1 C40c to +85c 28-lead thin shrink small outline [tssop] ru-28 EVAL-AD7765EBZ 1 evaluation board 1 z = rohs compliant part.
ad7765 rev. 0 | page 30 of 32 notes
ad7765 rev. 0 | page 31 of 32 notes
ad7765 rev. 0 | page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06519-0-6/07(0)

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